On minimizing memory in systolic arrays for the dynamic time warping algorithm

Authors:
E. Dijkstra;C. Piguet
Affiliations:
-;-
Venue:
Integration, the VLSI Journal
Year:
1986

Citing 8
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Abstract

New systolic architectures have been evaluated for the Dynamic Time Warping (DTW) algorithm. This algorithm is a non-linear pattern matching technique used in isolated and continuous speech recognition systems. The proposed systolic decomposition for the DTW algorithm combines simultaneously (1) simple and regular systolic communication schemes and (2) a decomposition strategy which aims at a minimum amount of memory. This approach has led to a systolic architecture which is relatively flexible, compact and easy to test. Several arrays can be built up by keeping the same decomposition of the DTW-algorithm. This allows an easy exchange, depending on the desired application, of execution speed against chip-area.