Principles of artificial intelligence
Principles of artificial intelligence
An efficient context-free parsing algorithm
Communications of the ACM
Introduction to VLSI Systems
Introduction to Formal Language Theory
Introduction to Formal Language Theory
Hardware for searching very large text databases
CAW '80 Proceedings of the fifth workshop on Computer architecture for non-numeric processing
On line context free language recognition in less than cubic time(Extended Abstract)
STOC '76 Proceedings of the eighth annual ACM symposium on Theory of computing
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Parallel parsing on a one-way array of finite-state machines
IEEE Transactions on Computers
A bibliography on parallel parsing
ACM SIGPLAN Notices
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
PUMPS Architecture for Pattern Analysis and Image Database Management
IEEE Transactions on Computers
VLSI Array Design Under Constraint of Limited I/O Bandwidth
IEEE Transactions on Computers
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This paper presents two VLSI architectures for the recognition of context-free languages and finite-state languages. The architecture for context-free languages consists of n(n+1)/2 identical cells and it is capable of recognizing an input string of length n in 2n time units. The architecture for finite-state languages consists of n cells and it can recognize a string of length n in constant time. Since both architectures have characteristics such as modular layout, simple constrol and dataflow pattern, high degree of multiprocessing and/or pipelining, etc., they are very suitable for VLSI implementation.