Introduction to Formal Language Theory
Introduction to Formal Language Theory
VLSI architectures for high speed recognition of context-free languages and finite-state languages
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Effects of cache coherency in multiprocessors
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Efficient interprocessor communication for MIMD multiprocessor systems
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
An adaptive multimicroprocessor array computing structure for radar signal processing applications
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Architectural features of CASSM: A Context Addressed Segment Sequential Memory
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Current research into specialized processors for text information retrieval
VLDB '78 Proceedings of the fourth international conference on Very Large Data Bases - Volume 4
VLSI Performance Comparison of Banyan and Crossbar Communications Networks
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
Direct A Multiprocessor Organization for Supporting Relational Database Management Systems
IEEE Transactions on Computers
DBC A Database Computer for Very Large Databases
IEEE Transactions on Computers
RAP.2 An Associative Processor for Databases and Its Applications
IEEE Transactions on Computers
A Design of a Fast Cellular Associative Memory for Ordered Retrieval
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Partitioned Matrix Algorithms for VLSI Arithmetic Systems
IEEE Transactions on Computers
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
Pluribus: a reliable multiprocessor
AFIPS '75 Proceedings of the May 19-22, 1975, national computer conference and exposition
DIALOG: a distributed processor organization for database machine
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
Image understanding architectures
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
Distributed scheduling of resources on interconnection networks
AFIPS '82 Proceedings of the June 7-10, 1982, national computer conference
A multiaccess bus arbitration scheme for VLSI-densed distributed systems
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
A Comparative Study of Distributed Resource Sharing on Multiprocessors
IEEE Transactions on Computers
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The PUMPS architecture consists of P task processing units (TPU) which share a pool of special peripheral processors, VLSI functional units, and a common two-dimensional shared memory (SM) via a block transfer oriented interconnection network. A shared cache is provided between the TPU's and SM for efficient MIMD interprocessor communication. The SM is also connected via a backend database management network (BDMN) with distributed control to the file memories, which are disk-based database storage devices.