Dynamic storage allocation in the Atlas computer, including an automatic use of a backing store
Communications of the ACM
An Investigation of Alternative Cache Organizations
IEEE Transactions on Computers
Considerations in block-oriented systems design
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
Cache system design in the tightly coupled multiprocessor system
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
Structural aspects of the system/360 model 85: I general organization
IBM Systems Journal
Structural aspects of the system/360 model 85: II the cache
IBM Systems Journal
Sequential consistency versus linearizability (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
A correctness condition for high-performance multiprocessors (extended abstract)
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
Simple compiler algorithms to reduce ownership overhead in cache coherence protocols
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
PODC '94 Proceedings of the thirteenth annual ACM symposium on Principles of distributed computing
Memory access buffering in multiprocessors
25 years of the international symposia on Computer architecture (selected papers)
On the inclusion properties for multi-level cache hierarchies
25 years of the international symposia on Computer architecture (selected papers)
On Message.Dependent Deadlocks in Multiprocessor/Multicomputer Systems
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Hybrid compiler/hardware prefetching for multiprocessors using low-overhead cache miss traps
ICPP '97 Proceedings of the international Conference on Parallel Processing
An adaptive sequential prefetching scheme in shared-memory multiprocessors
ICPP '97 Proceedings of the international Conference on Parallel Processing
Formal Verification of Delayed Consistency Protocols
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
The Combined Effectiveness of Unimodular Transformations, Tiling, and Software Prefetching
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Serializability, Concurrency Control, and Replication Control
Selected papers from the Eight International Workshop on Foundations of Models and Languages for Data and Objects, Transactions and Database Dynamics
An Adaptive Limited Pointers Directory Scheme for Cache Coherence of Scalable Multiprocessors
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Scalability in computing for today and tomorrow
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Effectiveness of hardware-based stride and sequential prefetching in shared-memory multiprocessors
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Relaxing Cache Coherence Protocol with QOLB Synchronizations
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
An effective full-map directory scheme for the sectored caches
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Hybrid Full Map Directory Scheme for Distributed Shared Memory Multiprocessors
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
A Distributed Cache Coherence Protocol for Hypercube Multiprocessors
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Reducing the Write Traffic for a Hybrid Cache Protocol
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Cache coherency communication cost in a NoC-based MPSoC platform
Proceedings of the 20th annual conference on Integrated circuits and systems design
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
Shared Cache for Multiple-Stream Computer Systems
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
PUMPS Architecture for Pattern Analysis and Image Database Management
IEEE Transactions on Computers
Effects of Cache Coherency in Multiprocessors
IEEE Transactions on Computers
The case for simple, visible cache coherency
Proceedings of the 2008 ACM SIGPLAN workshop on Memory systems performance and correctness: held in conjunction with the Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '08)
Comparison of memory write policies for NoC based multicore cache coherent systems
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Exploit temporal locality of shared data in SRC enabled CMP
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
Cohesion: a hybrid memory model for accelerators
Proceedings of the 37th annual international symposium on Computer architecture
WAYPOINT: scaling coherence to thousand-core architectures
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
SPACE: sharing pattern-based directory coherence for multicore scalability
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
A provably starvation-free distributed directory protocol
SSS'10 Proceedings of the 12th international conference on Stabilization, safety, and security of distributed systems
Research note: C-AMTE: A location mechanism for flexible cache management in chip multiprocessors
Journal of Parallel and Distributed Computing
A composite and scalable cache coherence protocol for large scale CMPs
Proceedings of the international conference on Supercomputing
Filtering directory lookups in CMPs with write-through caches
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
Filtering directory lookups in CMPs
Microprocessors & Microsystems
A new hybrid directory scheme for shared memory multi-processors
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
Computer Communications
An automatic code overlaying technique for multicores with explicitly-managed memory hierarchies
Proceedings of the Tenth International Symposium on Code Generation and Optimization
Complexity-effective multicore coherence
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Building expressive, area-efficient coherence directories
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
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A memory hierarchy has coherence problems as soon as one of its levels is split in several independent units which are not equally accessible from faster levels or processors. The classical solution to these problems, as found for instance in multiprocessor, multicache systems, is to restore a degree of interdependence between such units through a set of high speed interconnecting buses. This solution is not entirely satisfactory, as it tends to reduce the throughput of the memory hierarchy and to increase its cost.