A Distributed Cache Coherence Protocol for Hypercube Multiprocessors

Authors:
Yeimkunn Chang;Laxmi N. Bhuyan;Akhilesh Kumar
Affiliations:
Texas A&M University, USA;Texas A&M University, USA;Texas A&M University, USA
Venue:
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Year:
1994

Citing 6
Cited 0

Hierarchical cache/bus architecture for shared memory multiprocessors

ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons

ACM Computing Surveys (CSUR)
Design and Analysis of Cache Coherent Multistage Interconnection Networks

IEEE Transactions on Computers
Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors

IEEE Transactions on Parallel and Distributed Systems
Generalized Hypercube and Hyperbus Structures for a Computer Network

IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes a distributed directory cache coherence protocol and compares the performance of the proposed protocol with fully mapped and single linked list protocols for the hypercube multiprocessors. The directories of shared blocks are maintained as a tree structure which is motivated by the similarity of the indirect binary n-cube to the direct binary n-cube. The proposed protocol also takes advantage of the wormhole routing technique. Compared to the fully mapped and single linked list schemes, the proposed protocol reduces the memory reference latency and the network traffic.