Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Hierarchical cache/bus architecture for shared memory multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
An evaluation of directory schemes for cache coherence
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Memory-reference characteristics of multiprocessor applications under MACH
SIGMETRICS '88 Proceedings of the 1988 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Introducing memory into the switch elements of multiprocessor interconnection networks
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor
IEEE Transactions on Computers
MVAMIN: mean value analysis algorithms for multistage interconnection networks
Journal of Parallel and Distributed Computing
Analysis of directory based cache coherence schemes with multistage networks
CSC '92 Proceedings of the 1992 ACM annual conference on Communications
Design and application of cache coherent multiprocessors
Design and application of cache coherent multiprocessors
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An economical solution to the cache coherence problem
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors
IEEE Transactions on Computers
Performance and Reliability of the Multistage Bus Network
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A Distributed Cache Coherence Protocol for Hypercube Multiprocessors
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
In-network coherence filtering: snoopy coherence without broadcasts
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
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A directory of state information is introduced into a multistage interconnection network (MIN) switch, and a multiple copy cache coherence protocol is developed. It is shown that the protocol is better than a single copy protocol on this MIN with directories (MIND) scheme. A network called the multistage bus network (MBN), which introduces a bus and multiple snoopers into the switches of a MIN, is presented. The snooping buses form multiple trees with the memories at the roots and the processors at the leaves. Each switch contains directories to hold state information on the shared blocks that is used to filter the coherence traffic from one level to another. The shared requests pass through the directories, whereas the private requests pass directly from the bus in one level to the bus in the next level. Analytical and simulation models for these multistage cache coherent architectures are developed. Both the MIND and the MBN schemes are studied with a simple multiple copy protocol. The results show that the MBN scheme performs better than the MIND or conventional scheme.