Hierarchical cache/bus architecture for shared memory multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Design and Analysis of Cache Coherent Multistage Interconnection Networks
IEEE Transactions on Computers
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
The NYU Ultracomputer Designing an MIMD Shared Memory Parallel Computer
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Design and Performance of Generalized Interconnection Networks
IEEE Transactions on Computers
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A Multistage Bus Network(MBN) has been proposed as a viable alternative to the existing interconnection networks. The MBN consists of multiple stages of buses connected in a manner similar to the conventional Multistage Interconnection Networks(MINs) and has the same bandwidth at each stage. Due to the bidirectional nature of the MBN, there exist a number of separate paths between any source and destination pair. Some paths make a U-turn at an intermediate stage switch which is a common ancestor of the source and destination. We present self routing techniques for the various paths. We also present a performance analysis of a synchronous packet switched MBN and compare the results with those of a MIN. Finally we present a reliability analysis of the MBN and show its superiority over the MIN.