A Fault-Tolerant Mapping Scheme for a Configurable Multiprocessor System
IEEE Transactions on Computers
Multistage Interconnection Network Reliability
IEEE Transactions on Computers
Failure Dependent Performance Analysis of a Fault-Tolerant Multistage Interconnection Network
IEEE Transactions on Computers
A cost-effective reliable multipath interconnection network
ACM SIGARCH Computer Architecture News
Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses
IEEE Transactions on Parallel and Distributed Systems
Design and Performance Analysis of Load-Distributing Fault-Tolerant Network
IEEE Transactions on Computers
Tolerating Multiple Faults in Multistage Interconnection Networks with Minimal Extra Stages
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Performance analysis and fault tolerance of randomized routing on Clos networks
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Analysis of a multistage interconnection network using binary decision diagrams (BDD)
SRDS '96 Proceedings of the 15th Symposium on Reliable Distributed Systems
Performance and Reliability of the Multistage Bus Network
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Journal of Discrete Algorithms
Reliability analysis of multi-path multi-stage interconnection network
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
Modified composite Banyan network with an enhanced terminal reliability
Computer Communications
A fault-tolerant 2*2 switching element for switching networks
Computer Communications
| Hi-index | 4.12 |
First Page of the Article