Design and analysis of fault-tolerant multistage interconnection networks with low link complexity
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Reliability of Computer Systems and Networks: Fault Tolerance,Analysis,and Design
Reliability of Computer Systems and Networks: Fault Tolerance,Analysis,and Design
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
A Survey of Interconnection Networks
Computer
The Journal of Supercomputing
Stochastic communication for application-specific Networks-on-Chip
The Journal of Supercomputing
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In this paper, we examine the reliability of multi-path multi-stage interconnection networks (MINs) of different class. The bounded expressions for the time-dependent reliability for 16 × 16 Zeta Networks (ZTNs) and 16 × 16 Augmented Shuffle-Exchange Networks (ASENs) are derived. Furthermore, reliability upper bound and lower bound that is useful for the analysis of large networks is derived. The "full-access" criterion and "dead-fault" model is used for the reliability analysis. All numerical and simulation results for networks as large as 512 × 512 are provided. The studies of hardware cost and cost-effectiveness have also been carried out for network size as large as 512 × 512. The simulation study reveals that ZTNs are better in terms of cost and cost-effectiveness while both networks are equally reliable in terms of upper bounds.