High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Compartmental Modeling with Networks
Compartmental Modeling with Networks
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
On Path-length and Routing-tag Algorithm for Hybrid Irregular Multi-stage Interconnection Networks
SNPD '07 Proceedings of the Eighth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing - Volume 01
Journal of Discrete Algorithms
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
UKSIM '09 Proceedings of the UKSim 2009: 11th International Conference on Computer Modelling and Simulation
The Journal of Supercomputing
Reliability analysis of multi-path multi-stage interconnection network
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
The Journal of Supercomputing
Journal of Electrical and Computer Engineering
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In this paper, we have developed analytical stochastic communication technique for inter and intra-Networks-on-Chip (NoC) communication. It not only separates the computation and communication in Networks-in-Package (NiP) but also predicts the communication performance. Moreover, it will help in tracking of the lost data packets and their exact location during the communication. Further, the proposed technique helps in building the Closed Donor Controlled Based Compartmental Model, which helps in building Stochastic Model of NoC and NiP. This model helps in computing the transition probabilities, latency, and data flow from one IP to other IP in a NoC and among NoCs in NiP. From the simulation results, it is observed that the transient and steady state response of transition probabilities give state of data flow latencies among the different IPs in NoC and among the compartments of NoCs in NiP. Furthermore, the proposed technique produces low latency as compared to the latencies being produced by the existing topologies.