Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks
IEEE Transactions on Computers - The MIT Press scientific computation series
Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor
IEEE Transactions on Computers
IEEE Transactions on Computers
Multimicroprocessor Systems
Fault-tolerant wafer-scale architectures for VLSI
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Study of multistage SIMD interconnection networks
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
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A fault-tolerant mapping scheme for a configurable multiprocessor system using multistage interconnection networks is presented. By adapting its interprocessor connections, the multiprocessor system can provide many regular topological configurations suitable for a variety of parallel computation applications. The configurability of the system is achieved by applying a set of configuration procedures to a linear address space of the system. The central idea behind the scheme is the use of two transformations to restore the linear address space in the presence of processor failures. The fault-tolerant mapping scheme is composed of three algorithms. The algorithms adaptively use the two transformations to handle three different types of faults: single faults, double faults, and triple or greater faults. It is shown that when there are a few processor failures, the algorithms can effectively achieve fault-free linear subspaces with graceful degradation.