High-performance computer architecture (2nd ed.)
High-performance computer architecture (2nd ed.)
Dynamic base register caching: a technique for reducing address bus width
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
A framework for adaptive routing in multicomputer networks
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
New layouts for the shuffle-exchange graph(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Information content of CPU memory referencing behavior
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
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A method of reducing the volume of data flowing through the network in a shared memory parallel computer (multiprocessor) is described. The reduction is achieved by difference coding the memory addresses in messages sent between processing elements (PE's) and memories. In an implementation, each PE would store the last address sent to each memory, and vice versa. Messages that would normally contain an address insteadcontain the difference between the address associated with the current and most recentmessages. Trace-driven simulation shows that only 70% or less of traffic volume(including data and overhead) is necessary, even in systems using coherent caches. Thereduction in traffic could result in a lower cost or lower latency network. The cost of thehardware to achieve this is small, and the delay added is insignificant compared tonetwork latency.