A complexity theory for VLSI
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
Hamiltonian Cycles in the Shuffle-Exchange Network
IEEE Transactions on Computers
Work-preserving emulations of fixed-connection networks
STOC '89 Proceedings of the twenty-first annual ACM symposium on Theory of computing
Optimal bounded-degree VLSI networks for sorting in a constant number of rounds
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses
IEEE Transactions on Parallel and Distributed Systems
Work-preserving emulations of fixed-connection networks
Journal of the ACM (JACM)
Constant Geometry Fast Fourier Transforms on Array Processors
IEEE Transactions on Computers
A layout strategy for VLSI which is provably good (Extended Abstract)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
IEEE Transactions on Computers
Two VLSI Structures for the Discrete Fourier Transform
IEEE Transactions on Computers
The VLSI Complexity of Sorting
IEEE Transactions on Computers
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In this extended abstract, we present several new layouts for the shuffle-exchange graph, including one which requires only 0(n2/log2n) area. The optimal layout is described and analyzed in section 3. The analysis is heavily dependent on several combinatorial results which we state in section 2 and prove in the appendix. The other layouts are described in section 4. Although these layouts are not asymptotically optimal (most require 0(n2/log3/2n) area), the theory behind their development is interesting and may eventually lead to good practical layouts as well as other asymptotically optimal layouts.