An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Information transfer and area-time tradeoffs for VLSI multiplication
Communications of the ACM
Introduction to VLSI Systems
New layouts for the shuffle-exchange graph(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
A CLASS OF FINITE COMPUTATION STRUCTURES SUPPORTING THE FAST FOURIER TRANSFORM
A complexity theory for VLSI
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
A combinatorial limit to the computing power of V.L.S.I. circuits
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
IEEE Transactions on Computers
A reconfigurable systolic array architecture for multicarrier wireless and multirate applications
International Journal of Reconfigurable Computing
Hi-index | 14.98 |
Two VLSI structures for the computation of the discrete Fourier transform are presented. The first structure is a pipeline working concurrently on different transforms. It is shown that it matches, within a constant factor, the theoretical lower bounds for area versus data rate. The second structure is a simple modification of the first one; it works on a single transform at a time, and it matches within a constant factor the theoretical area-time lower bounds.