Modular Architecture for High Performance Implementation of the FRR Algorithm
IEEE Transactions on Computers
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
Multirate Digital Signal Processing: Multirate Systems, Filter Banks, Wavelets
Multirate Digital Signal Processing: Multirate Systems, Filter Banks, Wavelets
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Two VLSI Structures for the Discrete Fourier Transform
IEEE Transactions on Computers
Computationally efficient systolic architecture for computing the discrete Fourier transform
IEEE Transactions on Signal Processing
Efficient VLSI architectures for fast computation of the discreteFourier transform and its inverse
IEEE Transactions on Signal Processing
Multidimensional systolic arrays for the implementation of discreteFourier transforms
IEEE Transactions on Signal Processing
High-speed and low-power split-radix FFT
IEEE Transactions on Signal Processing
A reconfigurable 8 GOP ASIC architecture for high-speed data communications
IEEE Journal on Selected Areas in Communications
Adaptive polyphase subband decomposition structures for image compression
IEEE Transactions on Image Processing
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A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time sharing computation of high-throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector-matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA-based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high-density computing.