Computationally efficient systolic architecture for computing the discrete Fourier transform

Authors:
J.G. Nash
Affiliations:
Centar, Los Angeles, CA, USA
Venue:
IEEE Transactions on Signal Processing
Year:
2005

Citing 0
Cited 2

A reconfigurable systolic array architecture for multicarrier wireless and multirate applications

International Journal of Reconfigurable Computing
Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications

Journal of Signal Processing Systems

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Abstract

A new high-performance systolic architecture for calculating the discrete Fourier transform (DFT) is described which is based on two levels of transform factorization. One level uses an index remapping that converts the direct transform into structured sets of arithmetically simple four-point transforms. Another level adds a row/column decomposition of the DFT. The architecture supports transform lengths that are not powers of two or based on products of coprime numbers. Compared to previous systolic implementations, the architecture is computationally more efficient and uses less hardware. It provides low latency as well as high throughput, and can do both one- and two-dimensional DFTs. An automated computer-aided design tool was used to find latency and throughput optimal designs that matched the target field programmable gate array structure and functionality.