VLSI array processors
Fast fourier transforms: a tutorial review and a state of the art
Signal Processing
Numerical recipes in C (2nd ed.): the art of scientific computing
Numerical recipes in C (2nd ed.): the art of scientific computing
A VLSI architecture for the real time computation of discrete trigonometric transforms
Journal of VLSI Signal Processing Systems - Application specific array processors
VLSI Signal Processing Systems
VLSI Signal Processing Systems
Low-cost unified architectures for the computation of discrete trigonometric transforms
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
Computer
Computationally efficient systolic architecture for computing the discrete Fourier transform
IEEE Transactions on Signal Processing
Efficient VLSI architectures for fast computation of the discreteFourier transform and its inverse
IEEE Transactions on Signal Processing
Multidimensional systolic arrays for the implementation of discreteFourier transforms
IEEE Transactions on Signal Processing
A new systolic realization for the discrete Fourier transform
IEEE Transactions on Signal Processing
| Hi-index | 0.00 |
In wireless communication, multiple receive-antennas are used with orthogonal frequency division multiplexing (OFDM) to improve the system capacity and performance. The discrete Fourier transform (DFT) plays an important part in such a system since the DFTs are required to be performed for the output of all those antennas separately. This paper presents area-time efficient systolic structures for one-dimensional (1-D) and two-dimensional (2-D) DFTs of general lengths. A low-complexity recursive algorithm based on Clenshaw's recurrence relation is formulated for the computation of 1-D DFT. The proposed algorithm is used further to derive a linear systolic array for the DFT. The concurrency of computation has been enhanced and complexity is minimized by the proposed algorithm where an N驴驴point DFT is computed via four inner-products of real-valued data of length 驴驴(N/2). The proposed 1-D structure offers significantly lower latency, twice the throughput, and involves nearly the same area-time complexity of the corresponding existing structures. The proposed algorithm for 1-D DFT is extended further to obtain a 2-D systolic structure for the 2-D DFT without involving any transposition operation.