A new systolic realization for the discrete Fourier transform

Authors:
D.C. Kar;V.V.B. Rao
Affiliations:
Dept. of Electr. Eng., North Dakota State Univ., Fargo, ND;-
Venue:
IEEE Transactions on Signal Processing
Year:
1993

Citing 0
Cited 2

Hardware Efficient Fast Computation of the Discrete Fourier Transform

Journal of VLSI Signal Processing Systems
Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications

Journal of Signal Processing Systems

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Abstract

A systolic array for the discrete Fourier transform (DFT) is proposed. In comparison with previous schemes, the proposed scheme reduces the number of multipliers required almost by half and thus saves a considerable amount of hardware