Adaptive signal processing
VLSI array processors
Discrete-time signal processing
Discrete-time signal processing
Multirate systems and filter banks
Multirate systems and filter banks
Low-power design techniques for high-performance CMOS adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
High-level algorithm and architecture transformations for DSP synthesis
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of an ASIP architecture for low-level visual elaborations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Synthesis of folded pipelined architectures for multirate DSP algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance of image and video processing with general-purpose processors and media ISA extensions
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay
Integration, the VLSI Journal
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering
Journal of VLSI Signal Processing Systems
Synthesis of ASIPs for DSP algorithms
Integration, the VLSI Journal
A computational engine for multirate FIR digital filtering
Signal Processing
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Speech and Audio Coding for Wireless and Network Applications
Speech and Audio Coding for Wireless and Network Applications
The GSM System for Mobile Communications
The GSM System for Mobile Communications
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Arbitrary Precision Arithmetic --- SIMD Style
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Synthesis of Configurable Architectures for DSP Algorithms
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
PROPHID: a heterogeneous multi-processor architecture for multimedia
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Convergence of the DLMS algorithm with decreasing step size
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 03
Low-power adaptive filter architectures and their application to51.84 Mb/s ATM-LAN
IEEE Transactions on Signal Processing
Convergence of the delayed normalized LMS algorithm with decreasingstep size
IEEE Transactions on Signal Processing
Low-power equalizer architectures for high speed modems
IEEE Communications Magazine
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware/software partitioning for multifunction systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Image and video coding-emerging standards and beyond
IEEE Transactions on Circuits and Systems for Video Technology
Fractal engine: an affine video processor core for multimedia applications
IEEE Transactions on Circuits and Systems for Video Technology
A software-based MPEG-4 video encoder using parallel processing
IEEE Transactions on Circuits and Systems for Video Technology
A reconfigurable systolic array architecture for multicarrier wireless and multirate applications
International Journal of Reconfigurable Computing
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Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.