Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
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The advances in VLSI technology, high-speed processor designs, Internet/Intranet implementations, broadband networks (ATM and ISDN), and compression standards (JPEG, MPEG, H.261, H.263, and G.273) are leading to the popularity of multimedia applications. Examples include video over the Internet, interactive TV, distance learning, telemedicine, and digital libraries. Visual media processing poses challenges from several perspectives, specifically from the points of view of real-time implementation and scalability. We first present an overview and categorization of the various architectural approaches for multimedia processing. The fundamental operations involved in a majority of visual processing tasks are then derived. We propose an affine transform-processor-core-based video processor architecture called the fractal engine that is capable of implementing the basic visual processing operations. The fractal engine is an open architecture, and is designed to be modular and scalable, and therefore has the potential to satisfy the heterogeneous computing requirements of the different media types in multimedia processing. Details of the individual modules of the fractal engine as well the implementation of the architecture in VHDL are also presented