Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
Low complexity FIR filters using factorization of perturbed coefficients
Proceedings of the conference on Design, automation and test in Europe
Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High speed FIR filters for digital decimation
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
| Hi-index | 0.25 |
In many DSP-based high-speed modem applications, such as broadband modems for high-speed Internet access to the home or gigabit Ethernet transceivers, channel equalization requires processing power so high that power consumption and clock speed become major design challenges. This article describes techniques to implement low-cost adaptive equalizers for ASIC implementations of broadband modems. Power consumption can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techniques. The derivation of a hybrid FIR filter structure is given that enables the designer to adjust both the speed and power consumption to suit an application. Furthermore, the architecture can be made programmable to target multiple applications in one piece of silicon while maintaining or even improving the efficiency of the architecture. Run-time techniques are shown that can minimize the power consumption for a given application or operating environment. In all cases, the power reduction techniques are supported by simulations and measurements made on a test integrated circuit