High speed FIR filters for digital decimation

Authors:
Marco Brambilla;Daniele Guidi;Valentino Liberali
Affiliations:
Micro System Architecturing, Agrate Brianza, Italy;Micro System Architecturing, Agrate Brianza, Italy;Università di Pavia, Dipartimento di Elettronica, Pavia, Italy
Venue:
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Year:
1999

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Abstract

This paper describes a multistage FIR decimation filter implemented with a multiplier-free architecture. The filter is designed to be used in ΣΔ A/D converters in submicron CMOS technology. The proposed architecture aims at increasing the operation speed while limiting the power dissipation, thus reducing the injection of switching noise into the substrate and the digital/analog crosstalk.