A reconfigurable dual output low power digital PWM power converter
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Design and implementation of a scalable encryption processor with embedded variable DC/DC converter
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering
Journal of VLSI Signal Processing Systems
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Modulation scaling for Energy Aware Communication Systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling
Proceedings of the 14th international symposium on Systems synthesis
Proceedings of the 14th international symposium on Systems synthesis
Quantifying and enhancing power awareness of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A survey of design techniques for system-level dynamic power management
Readings in hardware/software co-design
Energy-Scalable Protocols for Battery-Operated MicroSensor Networks
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
An adaptive low-power transmission scheme for on-chip networks
Proceedings of the 15th international symposium on System Synthesis
Energy efficient real-time scheduling
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Dynamic Power Management in Wireless Sensor Networks
IEEE Design & Test
Power management for energy-aware communication systems
ACM Transactions on Embedded Computing Systems (TECS)
Variable voltage task scheduling algorithms for minimizing energy/power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Iterative schedule optimization for voltage scalable distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Technology exploration for adaptive power and frequency scaling in 90nm CMOS
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 2004 international symposium on Low power electronics and design
An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip digital power supply control for system-on-chip applications
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy management for commodity short-bit-width microcontrollers
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
The Journal of Supercomputing
PROPHET: speculative load prediction algorithm for dynamic performance scaling
IWCMC '07 Proceedings of the 2007 international conference on Wireless communications and mobile computing
Design and architecture for an embedded 32-bit QueueCore
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Collaborative voltage scaling with online STA and variable-latency datapath
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Panoptic DVS: a fine-grained dynamic voltage scaling framework for energy scalable CMOS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Feedback fuzzy-PI control dynamic voltage scaling for real-time control tasks
ROBIO'09 Proceedings of the 2009 international conference on Robotics and biomimetics
Circuit modeling for practical many-core architecture design exploration
Proceedings of the 47th Design Automation Conference
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Variation resilient adaptive controller for subthreshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Optimized query routing trees for wireless sensor networks
Information Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low-power subthreshold to above threshold level shifters in 90nm and 65nm process
Microprocessors & Microsystems
Energy-aware wireless systems with adaptive power-fidelity tradeoffs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction level and operating system profiling for energy exposed software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-saving scheduling for weakly dynamic voltage scaling devices
WADS'05 Proceedings of the 9th international conference on Algorithms and Data Structures
Design exploration of energy-performance trade-offs for wireless sensor networks
Proceedings of the 49th Annual Design Automation Conference
Power-aware dynamic memory management on many-core platforms utilizing DVFS
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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The use of dynamically adjustable power supplies as a method to lower power dissipation in DSP is analyzed. Power can be reduced substantially without sacrificing performance in fixed-throughput applications by slowing the clock and lowering supply voltage instead of idling when computational workload varies. This can yield a typical power savings of 30-50%. If latency can be tolerated, buffering data and averaging processing rate can yield power reductions of an order of magnitude in some applications. Continuous variation of the supply voltage can be approximated by very crude quantization and dithering: a four-level controller is sufficient to get within a few percent of the optimal power savings. Significant savings are possible only if the voltage can be changed on the same time scale as the variations in workload. A chip has been fabricated and tested to verify the closed-loop functionality of a variable voltage system. The controller takes only 0.4 mm/sup 2/ and draws a maximum of 1 mW at 2 V with a 40 MHz clock. The control framework developed is applicable to generic DSP applications.