Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A low power switching power supply for self-clocked systems
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Low-Power CMOS Design
A completey on-chip voltage regulation technique for low power digital circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
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Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of ∼10%, and a 23% reduction in power after policy optimization.