Statecharts: A visual formalism for complex systems
Science of Computer Programming
Hardware/software co-design with the HMS framework
Journal of VLSI Signal Processing Systems
A solution methodology for exact design space exploration in a three-dimensional design space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Quantifying and enhancing power awareness of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Readings in hardware/software co-design
Readings in hardware/software co-design
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Functional verification of the superscalar SH-4 microprocessor
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
The Design of a Register Renaming Unit
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme
HPCASIA '04 Proceedings of the High Performance Computing and Grid in Asia Pacific Region, Seventh International Conference
Parallel Queue Processor Architecture Based on Produced Order Computation Model
The Journal of Supercomputing
Efficient design exploration based on module utility selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The QC-2 parallel Queue processor architecture
Journal of Parallel and Distributed Computing
A new code generation algorithm for 2-offset producer order queue computation model
Computer Languages, Systems and Structures
Dual-execution mode processor architecture
The Journal of Supercomputing
Design and implementation of a queue compiler
Microprocessors & Microsystems
Efficient compilation for queue size constrained queue processors
Parallel Computing
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
Using NoC routers as processing elements
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Compiling for Reduced Bit-Width Queue Processors
Journal of Signal Processing Systems
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Dual-execution mode processor architecture for embedded applications
Journal of Mobile Multimedia
The Journal of Supercomputing
On the design of a dual-execution modes processor: architecture and preliminary evaluation
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
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Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs especially for newly proposed architectures. This paper presents a prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using a hardware description language, we have created the Synthesizable model of a produced order parallel queue processor core for the integer subset parallel Queue architecture. A prototype implementation is produced by synthesizing the high-level model for the Stratix FPGA prototyping board. We show how to perform prototyping and optimizations to fully exploit the capabilities of the prototyped Queue processor core, while maintaining a common source base.