An efficient code generation algorithm for code size reduction using 1-offset P-code queue computation model

Authors:
Arquimedes Canedo;Ben A. Abderazek;Masahiro Sowa
Affiliations:
Graduate School of Information Systems, University of Electro-Communications, Chofu-Shi, Tokyo, Japan;Graduate School of Information Systems, University of Electro-Communications, Chofu-Shi, Tokyo, Japan;Graduate School of Information Systems, University of Electro-Communications, Chofu-Shi, Tokyo, Japan
Venue:
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Year:
2007

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Abstract

Embedded systems very often demand small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a dual instruction set. This approach reduces code size at the cost of performance degradation due to the greater number of reduced width instructions required to execute the same task. We propose a novel alternative for reducing code size by using a single reduced instruction set queue machine. We present a efficient code generation algorithm to insert additional instructions to be able to execute programs in the reduced instruction set. Our experiments show that the insertion of additional instructions is minimal and we demonstrate improved code size reduction of 16% over MIPS16, 26% over Thumb, and 50% over MIPS32 code. Furthermore, we show that our compiler without any optimization is able to extract about the same parallelism than fully optimized RISC code.