Parallel Queue Processor Architecture Based on Produced Order Computation Model

Authors:
Masahiro Sowa;Ben A. Abderazek;Tsutomu Yoshinaga
Affiliations:
Graduate School of Information Systems, The University of Electro-Communications, Tokyo, Japan 182-8585;Graduate School of Information Systems, The University of Electro-Communications, Tokyo, Japan 182-8585;Graduate School of Information Systems, The University of Electro-Communications, Tokyo, Japan 182-8585
Venue:
The Journal of Supercomputing
Year:
2005

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Abstract

This paper proposes novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a first-in-first-out (FIFO) circular queue-registers instead of random access registers. Datum is inserted in the queue-registers in produced order scheme and can be reused. We show that this feature has profound implications in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed.Our performance evaluations show a significant performance improvement (e.g., 10 to 26% decrease in program size and 6 to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.