Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Stack computers: the new wave
Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Scheduling tree-dags using FIFO queues: a control-memory trade-off
Journal of Parallel and Distributed Computing
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
Stack and Queue Layouts of Directed Acyclic Graphs: Part I
SIAM Journal on Computing
The Generation of Optimal Code for Stack Machines
Journal of the ACM (JACM)
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Queue Machines: Hardware Compilation in Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Parallel Queue Processor Architecture Based on Produced Order Computation Model
The Journal of Supercomputing
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
The Journal of Supercomputing
The QC-2 parallel Queue processor architecture
Journal of Parallel and Distributed Computing
Design and implementation of a queue compiler
Microprocessors & Microsystems
Efficient compilation for queue size constrained queue processors
Parallel Computing
Compiling for Reduced Bit-Width Queue Processors
Journal of Signal Processing Systems
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Queue computing is an attractive alternative for the compulsive demand of high-performance architectures. Code generation for queue machines has some problems but the solutions have not been studied thoroughly. A new parallel queue computation model, 2-offset P-Code queue computation model, is presented together with a new code generation algorithm. The code generation algorithm takes leveled DAGs as input and produces 2-offset P-Code assembly. We also developed a queue compiler to evaluate the new algorithm and compiled a set of C language benchmark programs for the 2-offset P-Code. The queue compiler generates between 8.55% less instructions and 10.55% more instructions than an actual MIPS32 compiler for the compiled programs.