The QC-2 parallel Queue processor architecture

Authors:
Ben A. Abderazek;Arquimedes Canedo;Tsutomu Yoshinaga;Masahiro Sowa
Affiliations:
Parallel and Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-Communications, 1-5-1 Chofu-shi, 1828585 Tokyo, Japan;Parallel and Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-Communications, 1-5-1 Chofu-shi, 1828585 Tokyo, Japan;Parallel and Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-Communications, 1-5-1 Chofu-shi, 1828585 Tokyo, Japan;Parallel and Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-Communications, 1-5-1 Chofu-shi, 1828585 Tokyo, Japan
Venue:
Journal of Parallel and Distributed Computing
Year:
2008

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Abstract

Queue based instruction set architecture processor offers an attractive option in the design of embedded systems. In our previous work, we proposed a novel queue processor architecture as a starting point for hardware/software design space exploration for embedded applications. In this paper, we present a high performance 32-bit Synthesizable QueueCore (QC-2)-an improved and optimized version of the produced order parallel Queue processor (PQP), with single precision floating-point support. The QC-2 core also implements a novel technique used to extend immediate values and memory instruction offsets that were otherwise not representable because of bit-width constraints in the PQP processor. A prototype implementation is produced by synthesizing the high-level model for a target FPGA device. We present the architecture description and design results in a fair amount of details.