A Framework for Microprocessor Correctness Statements
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
The QC-2 parallel Queue processor architecture
Journal of Parallel and Distributed Computing
Automatic verification of safety and liveness for pipelined machines using WEB refinement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
A functional approach to worst-case execution time analysis
WFLP'11 Proceedings of the 20th international conference on Functional and constraint logic programming
FOPARA'11 Proceedings of the Second international conference on Foundational and Practical Aspects of Resource Analysis
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This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM processors, uses features such as a 5-stage instruction pipeline, predicated execution, forwarding logic and multi-cycle instructions. The instruction set of the processor was defined as a set of abstract assertions. An implementation mapping was used to relate the abstract states in these assertions to detailed circuit states in the gate-level implementation of the processor. Symbolic Trajectory Evaluation was used to verify that the circuit fulfills each abstract assertion under the implementation mapping. The verification was done concurrently with the design implementation of the processor. Our verification did uncover 4 bugs that were reported back to the designer in a timely manner.