The QC-2 parallel Queue processor architecture
Journal of Parallel and Distributed Computing
A new code generation algorithm for 2-offset producer order queue computation model
Computer Languages, Systems and Structures
Dual-execution mode processor architecture
The Journal of Supercomputing
Design and implementation of a queue compiler
Microprocessors & Microsystems
Efficient compilation for queue size constrained queue processors
Parallel Computing
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
Dual-execution mode processor architecture for embedded applications
Journal of Mobile Multimedia
The Journal of Supercomputing
Hardware synthesis of recursive functions through partial stream rewriting
Proceedings of the 49th Annual Design Automation Conference
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In this paper, we hypothesize that reconfigurable computing is not more widely used because of the logistical difficulties caused by the close coupling of applications and hardware platforms. As an alternative, we propose computing machines that use a single, serial instruction representation for the entire reconfigurable computing application. We show how it is possible to convert, at run-time, the parallel portions of the application into a spatial representation suitable for execution on a reconfigurable fabric. The conversion to spatial representation is facilitated by the use of an instruction set architecture based on an operand queue. We describe techniques to generate code for queue machines and hardware virtualization techniques necessary to allow any application to execute on any platform.