Dual-execution mode processor architecture for embedded applications

Authors:
Md. Musfiquzzaman Akanda;Ben A. Abderazek;Masahiro Sowa
Affiliations:
Network Computing Laboratory, Graduate School of Information Systems, National University of Electro-communications, Tokyo, Japan;Adaptive Systems Laboratory, The University of Aizu, Aizu-Wakamatsu, Japan;Network Computing Laboratory, Graduate School of Information Systems, National University of Electro-communications, Tokyo, Japan
Venue:
Journal of Mobile Multimedia
Year:
2007

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Abstract

This paper presents a novel embedded 32-bit processor architecture targeted for mobile and embedded applications. The processor supports Queue and Stack based programming models in a single simple core. The design focuses on the ability to efficiently execute Queue programs and also to support Stack programs without a considerable increase in hardware to the base Queue architecture. A prototype implementation of the processor is produced by synthesizing the high level model for a target FPGA device. We present the architecture description and design results in a fair amount of details. From the design and evaluation results, the QSP32 core efficiently executes both Queue and Stack based programs and achieves on average about 65MHz speed. In addition, when compared to the base single-mode architecture (PQP), the QSP32 core requires only about 2.54% additional hardware.