Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme

  • Authors:

  • Ben A. Abderazek;M. Arsenji;Soichi Shigeta;Tsutomu Yoshinaga;Masahiro Sowa

  • Affiliations:

  • The University of electro-Communications, Japan;The University of electro-Communications, Japan;The University of electro-Communications, Japan;The University of electro-Communications, Japan;The University of electro-Communications, Japan

  • Venue:
  • HPCASIA '04 Proceedings of the High Performance Computing and Grid in Asia Pacific Region, Seventh International Conference
  • Year:
  • 2004

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Abstract

This paper proposes novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a FIFO queue registers instead of random access registers. Datum is inserted in the queue in produced order scheme and can be reused. We will show that this feature has a profound implication in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed. Our preliminary performance evaluations have shown a significant performance improvement (e.g., 10% to 26% decrease in program size and 6% to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.