Modular design structure and high-level prototyping for novel embedded processor core

Authors:
Ben A. Abderazek;Sotaro Kawata;Tsutomu Yoshinaga;Masahiro Sowa
Affiliations:
Graduate School of Information Systems, The University of Electro-Communications, Tokyo, Japan;Graduate School of Information Systems, The University of Electro-Communications, Tokyo, Japan;Graduate School of Information Systems, The University of Electro-Communications, Tokyo, Japan;Graduate School of Information Systems, The University of Electro-Communications, Tokyo, Japan
Venue:
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Year:
2005

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Abstract

In this research work, we present a high-level prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using modular design structure with control logic implemented as a set of communicating state machines, we show hardware emulation and optimizations results of a parallel queue proecssor architecture (QueueCore). We also show how to to fully exploit the capabilities of the designed QueueCore, while maintaining a common source base. From the evaluation results, we show that the QueueCore prototype fits on a single conventional FPGA device, thereby obviating the need to perform multi-chip partitioning which results in a loss of resource efficiency.