Estimating architectural resources and performance for high-level synthesis applications
DAC '93 Proceedings of the 30th international Design Automation Conference
Hardware/software co-design with the HMS framework
Journal of VLSI Signal Processing Systems
A solution methodology for exact design space exploration in a three-dimensional design space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded power supply for low-power DSP
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Verification of a microprocessor using real world applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Readings in Hardware/Software Co-Design
Readings in Hardware/Software Co-Design
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
Queue Processor Architecture for Novel Queue Computing Paradigm Based on Produced Order Scheme
HPCASIA '04 Proceedings of the High Performance Computing and Grid in Asia Pacific Region, Seventh International Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Parallel Queue Processor Architecture Based on Produced Order Computation Model
The Journal of Supercomputing
Exploring technology alternatives for nano-scale FPGA interconnects
Proceedings of the 42nd annual Design Automation Conference
Optimum State Assignment for Synchronous Sequential Circuits
IEEE Transactions on Computers
Efficient design exploration based on module utility selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and implementation of a queue compiler
Microprocessors & Microsystems
Efficient compilation for queue size constrained queue processors
Parallel Computing
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
Compiling for Reduced Bit-Width Queue Processors
Journal of Signal Processing Systems
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
The Journal of Supercomputing
| Hi-index | 0.00 |
Queue based instruction set architecture processor offers an attractive option in the design of embedded systems by providing high performance for a specific application. This work describes the design results and methodology of a queue processor core, named QueueCore, as a starting point for application-specific processor (ASP) design. By using simple and common base queue instruction set, the design space exploration is focused on the application-specific aspects of performance. In any new architecture, verification, which usually requires complicated and lengthy software simulation of an emulated model, is an important aspect. We show how cooperative hardware emulation, based on programmable logic, can be integrated into a co-design flow to evaluate the performance of the novel QueueCore processor and to verify the functional correctness of a specific benchmark on the system core. To avoid duplication of the design effort, different target implementations are derived from a common source. We present the evaluation results of the QueueCore for three different platforms.