Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Stack computers: the new wave
MIPS RISC architectures
Advanced compiler design and implementation
Advanced compiler design and implementation
Evolution and evaluation of SPEC benchmarks
ACM SIGMETRICS Performance Evaluation Review
Stack and Queue Layouts of Directed Acyclic Graphs: Part I
SIAM Journal on Computing
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Profile guided selection of ARM and thumb instructions
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Enhancing the performance of 16-bit code using augmenting instructions
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and Consumer Applications
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Proceedings of the conference on Design, automation and test in Europe
Parallel Queue Processor Architecture Based on Produced Order Computation Model
The Journal of Supercomputing
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
The Journal of Supercomputing
Microarchitecture and compiler techniques for dual width isa processors
Microarchitecture and compiler techniques for dual width isa processors
A new code generation algorithm for 2-offset producer order queue computation model
Computer Languages, Systems and Structures
Design and architecture for an embedded 32-bit QueueCore
Journal of Embedded Computing - Issues in embedded single-chip multicore architectures
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines
ISPAN '08 Proceedings of the The International Symposium on Parallel Architectures, Algorithms, and Networks
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Embedded systems are characterized by the requirement of demanding small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a reduced bit-width instruction set. This approach reduces the length of the instructions to improve code size. However, having less addressable registers by the reduced instructions, these architectures suffer a slight performance degradation as more reduced instructions are required to execute a given task. On the other hand, 0-operand computers such as stack and queue machines implicitly access their source and destination operands making instructions naturally short. Queue machines offer a highly parallel computation model, unlike the stack model. This paper proposes a novel alternative for reducing code size by using a queue-based reduced instruction set while retaining the high parallelism characteristics in programs. We introduce an efficient code generation algorithm to generate programs for our reduced instruction set. Our algorithm successfully constrains the code to the reduced instruction set with the addition of only 4% extra code, in average. We show that our proposed technique is able to generate about 16% more compact code than MIPS16, 26% over ARM/Thumb, and 50% over MIPS32 code. Furthermore, we show that our compiler is able to extract about the same parallelism than fully optimized RISC code.