An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs

  • Authors:

  • A. Halambi;A. Shrivastava;P. Biswas;N. Dutt;A. Nicolau

  • Affiliations:

  • Center for Embedded Computer Systems, Department of Information and Computer Science, University of California, Irvine, CA;Center for Embedded Computer Systems, Department of Information and Computer Science, University of California, Irvine, CA;Center for Embedded Computer Systems, Department of Information and Computer Science, University of California, Irvine, CA;Center for Embedded Computer Systems, Department of Information and Computer Science, University of California, Irvine, CA;Center for Embedded Computer Systems, Department of Information and Computer Science, University of California, Irvine, CA

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2002

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Abstract

For many embedded applications, program code sizeis a critical design factor. One promising approach forreducing code size is to employ a "dual instruction set",where processor architectures support a normal (usually32 bit) Instruction Set, and a narrow, space-efficient(usually 16 bit) Instruction Set with a limited set of op-codes and access to a limited set of registers. This feature, however, requires compilers that can reduce codesize by compiling for both Instruction Sets. Existingcompiler techniques operate at the function-level gran-ularity and are unable to make the trade-off between in-creased register pressure (resulting in more spills)anddecreased code size. We present a profitability basedcompiler heuristic that operates at the instruction-levelgranularity and is able to effectively take advantage ofboth Instruction Sets. We also demonstrate improvedcode size reduction, for the MIPS 32/16 bit ISA, usingour technique. Our approach more than doubles thecode size reduction achieved by existing compilers.