Code selection through object code optimization
ACM Transactions on Programming Languages and Systems (TOPLAS) - Lecture notes in computer science Vol. 174
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Profile guided selection of ARM and thumb instructions
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
ARM System Architecture
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
Enhancing the performance of 16-bit code using augmenting instructions
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and Consumer Applications
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
A Worst Case Timing Analysis Technique for Optimized Programs
RTCSA '98 Proceedings of the 5th International Conference on Real-Time Computing Systems and Applications
Embedded System Design Framework for Minimizing Code Size and Guaranteeing Real-Time Requirements
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Communications of the ACM - Program compaction
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Proceedings of the conference on Design, automation and test in Europe
Target-specific Global Code Improvement: Principles and Applications
Target-specific Global Code Improvement: Principles and Applications
Tuning the WCET of Embedded Applications
RTAS '04 Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Hi-index | 0.00 |
Embedded systems are often constrained in terms of both code size and execution time, because of a limited amount of available memory and real-time nature of applications. A dual instruction set processor, which supports a reduced instruction set (16 bits/instruction), in addition to a full instruction set (32 bits/instruction), allows an opportunity for a tradeoff between these two design criteria. Specifically, while the reduced instruction set can be used to reduce code size by providing smaller instructions, a program compiled into the reduced instruction set typically runs slower than the same program compiled into the full instruction set. Motivated by this observation, we propose a code generation technique that exploits this tradeoff relationship by selectively using the two instruction sets for different sections in the program. The proposed technique, called selective code transformation, not only provides a mechanism to enable a flexible tradeoff between a program's code size and its execution time, but also facilitates program optimization toward enhancing its worst case performance. The results from our experiments show that our proposed technique can be effectively used to fine-tune an application program on a spectrum of code size and execution performance, which, in turn, enables a system-wide optimization on memory space and execution speed involving multiple applications.