Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
A real-time language with a schedulability analyzer
A real-time language with a schedulability analyzer
Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Crafting a compiler with C
MIPS RISC architectures
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Predicting deterministic execution times of real-time programs
Predicting deterministic execution times of real-time programs
Pipelined processors and worst case execution times
Real-Time Systems
ACM Computing Surveys (CSUR)
Register allocation by priority-based coloring
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
High Level Timing Specification of Instruction-Level Parallel Processors
High Level Timing Specification of Instruction-Level Parallel Processors
Aspects of cache memory and instruction buffer performance
Aspects of cache memory and instruction buffer performance
Real-Time Schedulability Tests for Preemptive Multitasking
WPDRTS Selected papers from the 4th workshop on Parallel and distributed real-time systems
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Performance re-engineering of embedded real-time systems
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Cache Aware Pre-Runtime Scheduling
Real-Time Systems
Cache-Conscious Limited Preemptive Scheduling
Real-Time Systems
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Low-energy intra-task voltage scheduling using static timing analysis
Proceedings of the 38th annual Design Automation Conference
Generating Decision Trees for Decoding Binaries
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Automatic time-bound analysis for a higher-order language
PEPM '02 Proceedings of the 2002 ACM SIGPLAN workshop on Partial evaluation and semantics-based program manipulation
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
Automatic Accurate Cost-Bound Analysis for High-Level Languages
IEEE Transactions on Computers
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
ILP-Based Interprocedural Path Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Real-Time Program Refinement Using Auxiliary Variables
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
The estimation of the WCET in super-scalar real-time system
Real-time system security
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Abstraction of assembler programs for symbolic worst case execution time analysis
Proceedings of the 41st annual Design Automation Conference
Modeling control speculation for timing analysis
Real-Time Systems
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Scalable precision cache analysis for preemptive scheduling
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Principles of Timing Anomalies in Superscalar Processors
QSIC '05 Proceedings of the Fifth International Conference on Quality Software
A theory for execution-time derivation in real-time programs
Theoretical Computer Science - Quantitative aspects of programming languages (QAPL 2004)
Journal of Parallel and Distributed Computing
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Performance analysis based upon complete profiles
Proceedings of the 2006 conference on Specification and verification of component-based systems
Procedures and parameters in the real-time program refinement calculus
Science of Computer Programming
Selective code transformation for dual instruction set processors
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Cache modeling in probabilistic execution time analysis
Proceedings of the 45th annual Design Automation Conference
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Recent additions on the application programming interface of the TMO support middleware
Proceedings of the 13th Monterey conference on Composition of embedded systems: scientific and industrial issues
Modeling complex flows for worst-case execution time analysis
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
Ubiquitous verification of ubiquitous systems
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Cache-related preemption delay via useful cache blocks: Survey and redefinition
Journal of Systems Architecture: the EUROMICRO Journal
On using locking caches in embedded real-time systems
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Trace acquirement from real-time systems based on WCET analysis
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Coercing real-time refinement: a transmitter
1FACS'96 Proceedings of the 1st BCS-FACS conference on Northern Formal Methods
A catalog of stream processing optimizations
ACM Computing Surveys (CSUR)
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An accurate and safe estimation of a task驴s worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC驴s pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timingschema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach.