Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Realistic parallel performance estimation
Parallel Computing - Special double issue on environment and tools for parallel scientific computing
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A Co-processor System with a Virtex FPGA for Evolutionary Computation
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Configuration Caching and Swapping
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Accelerating Adobe Photoshop with the Reconfigurable Logic
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Acceleration of template-based ray casting for volume visualization using FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Modeling and mapping for dynamically reconfigurable hybrid architectures
Modeling and mapping for dynamically reconfigurable hybrid architectures
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The capabilities of general-purpose workstations are commonly enhanced by the addition of application-specific coprocessors located on the system expansion bus or a dedicated local bus. In order to determine the limits of applicability of such systems, performance estimation tools are required which are capable both of generating accurate predictions and supporting rapid evaluation of architectural alternatives. This paper describes a performance estimation method which meets these requirements. By combining data acquired using a variety of established techniques, and integrating these using a novel approach designed to capture far more of the intrinsic complexity of the system, extremely accurate estimates of performance can be generated. A detailed uncertainty analysis is provided, and the method is evaluated by comparing an application running on a coprocessor-enhanced workstation with model-based predictions, demonstrating estimation accuracy to be within 卤5% of measured values.