Use of elliptic curves in cryptography
Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
Optimal normal bases in GF(pn)
Discrete Applied Mathematics
Implementing elliptic curve cryptography
Implementing elliptic curve cryptography
Elliptic curves in cryptography
Elliptic curves in cryptography
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Elliptic Curve Public Key Cryptosystems
Elliptic Curve Public Key Cryptosystems
An Improved Algorithm for Arithmetic on a Family of Elliptic Curves
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Efficient Algorithms for Elliptic Curve Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Fast Key Exchange with Elliptic Curve Systems
CRYPTO '95 Proceedings of the 15th Annual International Cryptology Conference on Advances in Cryptology
A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Improvement of the Guajardo-Paar Method for Multiplication on Non-Supersingular Elliptic Curves
SCCC '98 Proceedings of the XVIII International Conference of the Chilean Computer Science Society
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
IEEE Transactions on Computers
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
An FPGA implementation of an elliptic curve processor GF(2m)
Proceedings of the 14th ACM Great Lakes symposium on VLSI
FPGA based hardware acceleration for elliptic curve public key cryptosystems
Journal of Systems and Software - Special issue: Rapid system prototyping
On-demand design service innovations
IBM Journal of Research and Development
Journal of VLSI Signal Processing Systems
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field
Journal of Systems Architecture: the EUROMICRO Journal
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Efficient finite field processor for GF(2163) and its implementation
International Journal of High Performance Systems Architecture
Novel approach design of elliptic curve cryptography implementation in VLSI
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
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Elliptic curve cryptography (ECC) has been the focus of much recent attention since it offers the highest security per bit of any known public key cryptosystem. This benefit of smaller key sizes makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this, paper a microcoded Xilinx Virtex based elliptic curve processor is described. In contrast to previous implementations, it implements curve operations as well as optimal normal basis field operations in F2n; the design is parameterized for arbitrary n; and it is microcoded to allow for rapid development of the control part of the processor. The design was successfully tested on a Xilinx Virtex XCV300-4 and, for n = 113 bits, utilized 1290 slices at a maximum frequency of 45 MHz and achieved a thirty-fold speedup over an optimized software implementation.