An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Factoring large numbers with programmable hardware
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automated target recognition on SPLASH 2
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Specifying and Compiling Applications for RaPiD
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
The Reconfigurable Streaming Vector Processor (RSVPTM)
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A loop accelerator for low power embedded VLIW processors
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Novel architecture for loop acceleration: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Integrating FPGAs in high-performance computing: introduction
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
The shunt: an FPGA-based accelerator for network intrusion prevention
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Attacking elliptic curve cryptosystems with special-purpose hardware
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
VEAL: Virtualized Execution Accelerator for Loops
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
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Attaching reconfigurable loop accelerator to a processor is a promising way to improve the performance and efficiency of the system. It's usually to unroll a loop to increase the parallelism of a loop accelerator. While the higher degree a loop is unrolled, the more reconfigurable area is needed. However, an observation is that the utilization of the loop accelerator is relative to the input. Focusing on the area and performance balance, a dynamically adaptive reconfigurable accelerator framework is proposed on CPU/RA architecture in the paper. Firstly, the inputs are classified into certain predefined types. At run-time the input of the application will be monitored and then the accelerator will be reconfigured to accomplish the area-performance dynamic adaption. An accelerator selection model is also presented to choose an accelerator at run-time according to the predefined input types. And a bzip2 case study is presented, the experimental results demonstrated the feasibility of the approach, and shown that up to 93.6% reconfigurable area is saved at a cost of 1.6% performance lost in a best case.