The data compression book (2nd ed.)
The data compression book (2nd ed.)
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Dependable Computing and Online Testing in Adaptive and Configurable Systems
IEEE Design & Test
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A fast hardware data compression algorithm and some algorithmic extensions
IBM Journal of Research and Development
Generalized kraft inequality and arithmetic coding
IBM Journal of Research and Development
Efficient VLSI for Lempel-Ziv compression in wireless data communication networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
Titan II: An IPcomp Processor for 10-Gbps Networks
IEEE Design & Test
A field programmable gate array media player for realmedia files
Journal of Computing Sciences in Colleges
Proceedings of the 45th annual Design Automation Conference
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and performance evaluation of an adaptive FPGA for network applications
Microelectronics Journal
Hardware vs. software implementations for calculating roots of polynomials
Journal of Computing Sciences in Colleges
A reverse-encoding-based on-chip bus tracer for efficient circular-buffer utilization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Data compression techniques based on Lempel-Ziv (LZ) algorithm are widely used in a variety of applications, especially in data storage and communications. However, since the LZ algorithm involves a considerable amount of parallel comparisons, it may be difficult to achieve a very high throughput using software approaches on general-purpose processors. In addition, error propagation due to single-bit transient errors during LZ compression causes a significant data integrity problem. In this paper, we present an implementation of LZ data compression on reconfigurable hardware with concurrent error detection for high performance and reliability. Our approach achieves 100Mbps throughput using four Xilinx 4036XLA FPGA chips. We have also presented an inverse comparison technique for LZ compression to guarantee data integrity with less area overhead than traditional systems based on duplication. The resulting execution time overhead and compression ratio degradation due to concurrent error detection is also minimized.