VLSI array processors
Text compression
Practical dictionary management for hardware data compression
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
DCC '95 Proceedings of the Conference on Data Compression
Performance optimization of wireless local area networks through VLSI data compression
Wireless Networks - Special issue VLSI in wireless networks
Journal of VLSI Signal Processing Systems
Dependable Computing and Online Testing in Adaptive and Configurable Systems
IEEE Design & Test
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Titan II: An IPcomp Processor for 10-Gbps Networks
IEEE Design & Test
A lossless data compression and decompression algorithm and its hardware architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a parallel algorithm, architecture, and implementation for efficient Lempel-Ziv (LZ)-based data compression. The parallel algorithm exhibits a scalable, parameterized, and regular structure and is well suited for VLSI array implementation. Based on our parallel algorithm and systematic design methodologies [8], two semisystolic array architectures have been developed which are low power and area efficient. The first architecture trades off the compression speed for the area and has a low run-time overhead for multichannel compression. The second architecture achieves a high compression rate (one data symbol per clock) at the expense of the area due to a large clock load and global wiring. Compared to a recent state-of-theart parallel architecture [14], our first array structure requires significantly less chip area (≅ 330 k versus ≅ 36 k transistors) and more than an order of magnitude less power (≅ 1.0 W versus ≅ 70 mW) while still providing the compression speed required for most data communication applications. Hence, data compression can be adopted in portable data communication as well as wireless local area networks. The second architecture has at least three times less area and power compared to [14] while providing the same constant compression rate. To demonstrate the correctness of our design, a prototype module for the first architecture has been implemented using 1.2 µ complementary metal-oxide-semiconductor (CMOS) technology. The compression module contains 32 simple and identical processors, has an average compression rate of 12.5 million bytes/s, and consumes 18.34 mW without the dictionary (≅ 70 mW with a 4.1k SRAM for the dictionary) while operating at a 100 MHz clock rate (simulated).