Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Fault-tolerant computer system design
Fault-tolerant computer system design
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Dependable Computing and Online Testing in Adaptive and Configurable Systems
IEEE Design & Test
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Transient errors and rollback recovery in LZ compression
PRDC '00 Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
Run-Time Management of Logic Resources on Reconfigurable Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The partial reconfiguration feature of some of the current-generation Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in on-chip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of FPGAs can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. Theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.