A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A formal approach to context scheduling for multicontext reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
Improving utilization of reconfigurable resources using two dimensional compaction
Proceedings of the conference on Design, automation and test in Europe
Improving utilization of reconfigurable resources using two-dimensional compaction
The Journal of Supercomputing
2D defragmentation heuristics for hardware multitasking on reconfigurable devices
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation of the whole system. The efficient management of the logic space available is one of the biggest problems faced by these systems. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. A rearrangement may be necessary to get enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A new software tool that helps to handle the problems posed by the consecutive reconfiguration of the same logic space is presented in this paper. This tool uses a novel on-line rearrangement procedure to solve fragmentation problems and to rearrange the logic space in a way completely transparent to the applications currently running.