A Complete Data Scheduler for Multi-Context Reconfigurable Architectures

Authors:
M. Sánchez-Élez;M. Férnandez;R. Maestre;F. Kurdahi;R. Hermida;N. Bagherzadeh
Affiliations:
Departamento de Arquitectura de Computadores y Automatica, Universidad Complutense - 28040 Madrid, SPAIN;Departamento de Arquitectura de Computadores y Automatica, Universidad Complutense - 28040 Madrid, SPAIN;Departamento de Arquitectura de Computadores y Automatica, Universidad Complutense - 28040 Madrid, SPAIN;Department of Electrical and Computer Engineering, University of California, Irvine, CA;Departamento de Arquitectura de Computadores y Automatica, Universidad Complutense - 28040 Madrid, SPAIN;Department of Electrical and Computer Engineering, University of California, Irvine, CA
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

A new technique is presented in this paper to improve theefficiency of data scheduling for multi-contextreconfigurable architectures targeting multimedia and DSPapplications. The main goal is to improve the applicationsexecution time minimizing external memory transfers.Some amount of on-chip data storage is assumed to beavailable in the reconfigurable architecture. Therefore theComplete Data Scheduler tries to optimally exploit thisstorage, saving data and result transfers between on-chipand external memories. In order to do this, specificalgorithms for data placement and replacement have beendesigned. We also show that a suitable data schedulingcould decrease the number of transfers required toimplement the dynamic reconfiguration of the system.