Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Low overhead fault-tolerant FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-line fault detection for bus-based field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Approach for Detecting Multiple Faulty FPGA Logic Blocks
IEEE Transactions on Computers
A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
RAM-based FPGA's: a test approach for the configurable logic
Proceedings of the conference on Design, automation and test in Europe
A formal approach to context scheduling for multicontext reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Universal Fault Diagnosis for Lookup Table FPGAs
IEEE Design & Test
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
On-Line Testable Logic Desgin for FPGA Implementation
Proceedings of the IEEE International Test Conference
BIST-Based Diagnostics of FPGA Logic Blocks
Proceedings of the IEEE International Test Conference
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of an Automatic Testing for FPGAs
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An efficient algorithm for finding empty space for online FPGA placement
Proceedings of the 41st annual Design Automation Conference
An embedded 1149.4 extension to support mixed-signal debugging
Microelectronics Journal
Progress in autonomous fault recovery of field programmable gate arrays
ACM Computing Surveys (CSUR)
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Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.