Field-programmable gate arrays
Field-programmable gate arrays
Testing of uncustomized segmented channel field programmable gate arrays
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
A Test Methodology Applied to Cellular Logic Programmable Gate Arrays
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Fault Modeling and Test Generation for FPGAs
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA
ATS '97 Proceedings of the 6th Asian Test Symposium
On the diagnosis of programmable interconnect systems: Theory and application
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testing the configurable interconnect/logic interface of SRAM-based FPGA's
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SRAM-Based FPGAs: Testing the Embedded RAM Modules
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Testing the Local Interconnect Resources of SRAM-Based FPGA's
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
A Specific Test Methodology for Symmetric SRAM-Based FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Different Experiments in Test Generation for XILINX FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs
Microelectronic Engineering
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel full coverage test method for CLBs in FPGA (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic Test Configurations to fully test the whole matrix of CLBs. In the proposed Test Configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of Test Configurations 8 is fixed and independent of the FPGA size.