RAM-based FPGA's: a test approach for the configurable logic
Proceedings of the conference on Design, automation and test in Europe
Minimizing the Number of Test Configurations for Different FPGA Families
ATS '99 Proceedings of the 8th Asian Test Symposium
Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's
ATS '02 Proceedings of the 11th Asian Test Symposium
ITC '02 Proceedings of the 2002 IEEE International Test Conference
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FPGA's configurability makes it difficult for FPGA's manufacturers to fully test it. In this paper, a full coverage test method for FPGA's Configurable Logic Blocks (CLBs) is proposed, through which all basic logics of FPGA's every CLB can be fully tested. Innovative test circuits are configured to build repeatable logic arrays for look-up tables, distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is implemented on different scales of Xilinx Virtex chips, where 19 test configuration circuits are needed to achieve 100% coverage for all CLBs. Besides, the method is transplantable and independent of FPGA's array size. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator - Turbofault is used to simulate FPGA's test coverage.